Advanced lithographic techniques such as 193 nm immersion lithography have been developed to achieve high quality and smaller feature sizes in microlithography processes, for purposes of forming ever smaller logic and memory transistors. It is important to achieve both smaller critical dimension (CD) in the imaged photoresist used in the microlithography process, and for the photoresists to provide both the lowest line edge roughness (LER) and line width roughness (LWR), while still retaining good process control tolerances such as high exposure latitude (EL) and a wide depth of focus (DOF).
The International Technology Roadmap for Semiconductors (ITRS) has recommended that feature LER (particularly for lines and trenches) should be no larger than 8% of CD, which with 65 nm features and smaller, is ever closer to the theoretical limit of LER that may be obtained based on the size of the polymer chains used in the photoresist. The design and practice of the combination of photoresist components are critical for the overall lithographic performance and the resist mixtures.
While a variety of photoacid generators (PAGs) used for formulating photoresists are found in the art, such as those disclosed in U.S. Pat. No. 7,304,175, photoresist compositions including such PAGs have not shown the improved LER performance necessary to meet the ITRS requirements.